BIOS-e820: 0009f000 @ 00000000 (usable) BIOS-e820: 0fef0000 @ 00100000 (usable) Scan SMP from c0000000 for 1024 bytes. Scan SMP from c009fc00 for 1024 bytes. Scan SMP from c00f0000 for 65536 bytes. Intel MultiProcessor Specification v1.4 Virtual Wire compatibility mode. OEM ID: OEM00000 Product ID: PROD00000000 APIC at: 0xfee00000 Processor #0 Pentium(tm) Pro APIC version 17 Floating point unit present. Machine Exception supported. 64 bit compare & exchange supported. Internal APIC present. Bootup CPU Processor #1 Pentium(tm) Pro APIC version 17 Floating point unit present. Machine Exception supported. 64 bit compare & exchange supported. Internal APIC present. Bus #0 is PCI Bus #1 is PCI Bus #2 is ISA I/O APIC #2 Version 17 at 0xFEC00000. Processors: 2 mapped APIC to ffffe000 (fee00000) mapped IOAPIC to ffffd0000 (fec00000) Detected 801850 kHz processor. Console: colour VGA+ 80x25 Calibrating delay loop... 1599.07 BogoMIPS Memory: 257716k/262080k available (984k kernel code, 424k reserved, 2872k data, 84k init) Dentry hash table entries: 32768 (order 6, 256k) Buffer cache hash table entries: 262144 (order 8, 1024k) Page cache hash table entries: 65536 (order 6, 256k) VFS: Diskquotas version dquot_6.4.0 initialized 256K L2 cache (8 way) CPU: L2 Cache: 256K Checking 386/387 coupling... OK, FPU using exception 16 error reporting. Checking 'hlt' instruction... OK. POSIX conformance testing by UNIFIX mtrr: v1.35a (19990819) Richard Gooch (rgooch@atnf.csiro.au) Intel machine check architecture supported. Intel machine check reporting enabled on CPU#0. 256K L2 cache (8 way) CPU: L2 Cache 256K per-CPU timeslice cutoff: 50.04 usecs. CPU#0: Intel Pentium III (Coppermine) stepping 03 Getting VERSION: 40011 Getting VERSION: 40011 Getting LVT0: 700 Getting LVT1: 400 Setup_APIC_clock() called. Calibrating APIC timer ... ..... 8018347 CPU clocks in 1 timer chip tick. ..... 1336390 APIC bus clocks in 1 timer chip tick. ..... CPU clock speed is 801.8347 MHz. ..... system bus clock speed is 133.6390 MHz. CPU map: 3 Booting processor 1 eip 2000 Setting warm reset code and vector. 1. 2. 3. Asserting INIT. Desserting INIT. Sending STARTUP #1. After apic_write. Before start apic_write. Statup point 1. Waiting for send to finish... CPU#1 waiting for CALLOUT +Sending STARTUP #2. After apic_write. Before start apic_write. Startup point #1. Waiting for send to finish... +After Startup. Before Callout 1. After Callout 1. CALLIN, before enable_local_APIC(). setup_APIC_clock() called. waiting for other CPU calibrating APIC ... done, continuing. Calibrating delay loop... 1602.35 BogoMIPS Stack at about cffebfa4 Intel machine check reporting enabled on CPU#1. 256K L2 cache (8 way) CPU: L2 Cache: 256K OK. CPU1: Intel Pentium III (Coppermine) stepping 03 CPU has booted. Before bogomips. Total of 2 processors activated (3201.43 BogoMIPS). Before bogocount – setting activated=1. Boot done. enabling symmetric IO mode... ...done. ENABLING IO-APIC IRQs init IO_APIC IRQs IO-APIC (apicid-pin) 2-0, 2-5, 2-9, 2-11, 2-15, 2-20, 2-21, 2-22, 2-23 not connected. number of MP IRQ sources: 20. number of IO-APIC #2 registers: 24. testing the IO APIC....................... IO APIC #2...... .... register #00: 02000000 ....... : physical APIC id: 02 .... register #01: 00170011 ....... : max redirection entries: 0017 ....... : IO APIC version: 0011 .... register #02: 00000000 ....... : arbitration: 00 .... IRQ redirection table: NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect: 00 000 00 1 0 0 0 0 0 0 00 01 000 00 0 0 0 0 0 1 1 59 02 0FF 0F 0 0 0 0 0 1 1 51 03 000 00 0 0 0 0 0 1 1 61 04 000 00 0 0 0 0 0 1 1 69 05 000 00 1 0 0 0 0 0 0 00 06 000 00 0 0 0 0 0 1 1 71 07 000 00 0 0 0 0 0 1 1 79 08 000 00 0 0 0 0 0 1 1 81 09 000 00 1 0 0 0 0 0 0 00 0a 000 00 0 0 0 0 0 1 1 89 0b 000 00 1 0 0 0 0 0 0 00 0c 000 00 0 0 0 0 0 1 1 91 0d 000 00 1 0 0 0 0 0 0 00 0e 000 00 0 0 0 0 0 1 1 99 0f 000 00 1 0 0 0 0 0 0 00 10 0FF 0F 1 1 0 1 0 1 1 A1 11 0FF 0F 1 1 0 1 0 1 1 A9 12 0FF 0F 1 1 0 1 0 1 1 B1 13 0FF 0F 1 1 0 1 0 1 1 B9 14 000 00 1 0 0 0 0 0 0 00 15 000 00 1 0 0 0 0 0 0 00 16 000 00 1 0 0 0 0 0 0 00 17 000 00 1 0 0 0 0 0 0 00 .............................. ..... done. checking TSC synchronization across CPUs: passed. Setting commenced=1, go go go mtrr: your CPUs had inconsistent variable MTRR settings mtrr: probably your BIOS does not setup all CPUs PCI: PCI BIOS revision 2.10 entry at 0xfb2d0 PCI: Using configuration type 1 PCI: Probing PCI hardware PCI->APIC IRQ transform: (B0,I7,P3) -> 19 PCI->APIC IRQ transform: (B0,I7,P3) -> 19 PCI->APIC IRQ transform: (B0,I12,P0) -> 18 PCI->APIC IRQ transform: (B0,I15,P0) -> 17 PCI->APIC IRQ transform: (B0,I16,P0) -> 18 PCI->APIC IRQ transform: (B0,I17,P0) -> 19 PCI->APIC IRQ transform: (B1,I0,P0) -> 16 Linux NET4.0 for Linux 2.2 Based upon Swansea University Computer Society NET3.039 NET4: Linux TCP/IP 1.0 for NET4.0 IP Protocols: ICMP, UDP, TCP, IGMP TCP: Hash tables configured (ehash 262144 bhash 65536) Starting kswapd v 1.5 Detected PS/2 Mouse Port. pty: 256 Unix98 ptys configured Real Time Clock Driver v1.09 RAM disk driver initialized: 16 RAM disks of 4096K size loop: registered device at major 7 Uniform Multi-Platform E-IDE driver Revision: 6.30 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx VP_IDE: IDE controller on PCI bus 00 dev 39 VP_IDE: chipset revision 16 VP_IDE: not 100% native mode: will probe irqs later ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx VP_IDE: VIA vt82c686a (rev 22) IDE UDMA66 controller on pci00:07.1 ide0: BM-DMA at 0xc000-0xc007, BIOS settings: hda:DMA, hdb:pio PDC20265: IDE controller on PCI bus 00 dev 60 PDC20265: chipset revision 2 PDC20265: not 100% native mode: will probe irqs later PDC20265: (U)DMA Burst Bit ENABLED Primary PCI Mode Secondary PCI Mode. ide1: BM-DMA at 0xdc00-0xdc07, BIOS settings: hdc:DMA, hdd:pio ide2: BM-DMA at 0xdc08-0xdc0f, BIOS settings: hde:pio, hdf:pio hda: FUJITSU MPG3102AH, ATA DISK drive ide0 at 0x1f0-0x1f7,0x3f6 on irq 14