Re: [patch] 2.4.0, 2.4.0-ac12: APIC lock-ups

From: Maciej W. Rozycki (
Date: Mon Feb 05 2001 - 05:32:59 EST

On Sat, 3 Feb 2001, [ISO-8859-1] Gérard Roudier wrote:

> Note that tampering the IO/APIC after initializations looks extremally
> ugly to me. In my opinion, only the local APIC was intended by Intel
> designers to be accessed by CPU after initialization (I may be wrong
> here).

 In "82489DX Datasheet" Intel explicitly points to masking and unmasking
an interrupt pin in an I/O APIC as one of three ways of controlling
incoming interrupts (other two being the Task Priority Register in a local
APIC and the IF flag in a CPU) at run time. So far this is about the only
exhaustive APIC architecture description (a few further hints are also
present in "AP-388 82489DX User's Manual" but the datasheet is mostly a
superset). I haven't seen any other APIC architecture description -- all
others are mostly register programming guidelines only.

 Neither of these documents are available online, AFAIK. Last year I
asked Intel if providing electronic copies is possible, but they replied
it's not.

+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+        e-mail:, PGP key available        +

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