Re: VT82C686A corruption with 2.4.x

From: Vojtech Pavlik (
Date: Thu Feb 01 2001 - 15:51:16 EST

On Thu, Feb 01, 2001 at 01:20:00PM -0500, Byron Stanoszek wrote:

> > On Thu, Feb 01, 2001 at 11:46:08AM -0500, Byron Stanoszek wrote:
> >
> > > Yeah, by bios does the same thing too on the Abit KT7(a).
> >
> > Ok, I'll remember this. This is most likely the cause of the problems
> > many people had with the KT7 in the past.
> What cause are you referring to? As far as I know, there are two options to
> increasing the FSB clock.. one increases both FSB+PCICLK, the other just
> increases FSB. If you increase the FSB only, it should keep PCICLK at a solid
> 33. (But I could be wrong, I've never tested that. I can tomorrow though.)

I mean that people can alter the PCI clock on these boards and that 33
doesn't to be always exactly 33 due to rounding errors if used with a
FSB other than 66 or 100 or 133.

Could it be that the PCI bus is not asynchronous, but only
pseudo-synchronous, allowing for divisors of 5, 4.5, 4, 3.5, 3, 2.5, 2?

> > The U33 chips do UDMA timing in PCICLK (T = 30ns @ 33MHz) increments, U66 in
> > PCICLK*2 (T = 15ns @ 33 MHz) increments, and for U100 it's assumed that
> > there is an external 100MHz clock fed to the chip, so that the UDMA timing is
> > in T = 10ns increments independent of the PCICLK. I'm not 100% sure about
> > the last, it might be just PCICLK*3 (T = 10ns @ 33 MHz). An experiment needs
> > to be carried out to verify this.
> I don't have a KT7A personally, I only have a KT7. Can anyone else with a KT7A
> verify this? By verify, I take it you mean to use idebus=33 and overclock
> PCICLK? :) At least that would determine if UDMA100 is based on PCI or an
> external 100MHz source.

Actually he should use the correct idebus= so that the Active/Recover
timings are correct. If KT7A doesn't work with UDMA at high PCI clocks
*even when* idebus= is correct would mean that the UDMA timing is in
1/(PCICLK*3) units instead of units of 10ns.

Anyone help us?

Vojtech Pavlik
SuSE Labs
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