> - A driver that blindly shoe-horns some value for the cache-line size must
> be fixed. Basically, it should not change the value if it is not zero and,
> at least, warn user if it has changed the value because it was zero.
>
> What are the strong reasons that let some POST softwares not fill properly
> the cache line size of PCI devices ?
In part because it is not required to, and on x86 because there may be no
PCI configuration before the OS loader completes
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This archive was generated by hypermail 2b29 : Fri Dec 15 2000 - 21:00:18 EST