> If/When x86 (or all?) architectures use this, will it make sense to
> remove the PCI space cache line setting from drivers ?
> Or is there borked hardware out there that require drivers to say
> "This cacheline size must be xxx bytes, anything else will break" ?
If there is surely the driver can override it again before enabling the
master bit or talking to the device ?
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This archive was generated by hypermail 2b29 : Fri Dec 15 2000 - 21:00:17 EST