Hi,
I noticed a lot of drivers are setting the PCI_CACHE_LINE_SIZE
themselves, some to L1_CACHE_BYTES/sizeof(u32), others
to arbitrary values (4, 8, 16).
Then I spotted that we have a routine in the PCI subsystem
(pdev_enable_device) that sets all these to L1_CACHE_BYTES/sizeof(u32)
Further digging revealed that this routine was not getting called.
On my Athlon box, I've noticed some devices are getting their
default values set to 8 (where (I think) it should be 16 ?)
Questions:
1. Is there reason for the drivers to be setting this themselves
to hardcoded values ?
2. Why is pdev_device_enable no longer used ?
regards,
Davej.
-- | Dave Jones <davej@suse.de> http://www.suse.de/~davej | SuSE Labs- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Fri Dec 15 2000 - 21:00:17 EST