Re: PCI-PCI bridges mess in 2.4.x

From: Richard Henderson (rth@twiddle.net)
Date: Wed Nov 08 2000 - 18:48:11 EST


On Thu, Nov 09, 2000 at 01:03:36AM +0300, Ivan Kokshaysky wrote:
> But actually I'm concerned that all this code doesn't work at all -
> see reports from Michal Jaegermann (the bridge acts as if it drops
> config space transactions randomly).

I have no idea what Michal is seeing. It does, however, work
just dandy on my rawhide:

-+-[01]-+-01.0
 | +-02.0-[02]----00.0
 | +-04.0
 | \-04.1
 \-[00]-+-01.0
        +-02.0
        \-05.0

01:02.0 PCI bridge: Digital Equipment Corporation DECchip 21050 (rev 02) \
                (prog-if 00 [Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- \
                Stepping- SERR- FastB2B-
        Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- \
                <TAbort- <MAbort- >SERR- <PERR-
        Latency: 248, cache line size 10
        Bus: primary=01, secondary=02, subordinate=02, sec-latency=0
        I/O behind bridge: 00009000-00009fff
        Memory behind bridge: 02300000-023fffff
        BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-

02:00.0 SCSI storage controller: Q Logic ISP1020 (rev 02)
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ \
                Stepping- SERR+ FastB2B-
        Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- \
                <TAbort- <MAbort- >SERR- <PERR-
        Latency: 248, cache line size 10
        Interrupt: pin A routed to IRQ 40
        Region 0: I/O ports at 200009000 [size=256]
        Region 1: Memory at 0000000202310000 (32-bit, non-prefetchable) [size=4K]
        Expansion ROM at 0000000202300000 [disabled] [size=64K]

Whee! We're back in Bootsville.

r~
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