Re: [PATCH][CFT] dcache-ac6-D - dcache threading

From: Alan Cox (
Date: Mon Jun 05 2000 - 06:52:02 EST

> For CONFIG_I386 CONFIG_X86_L1_CACHE_BYTES is 16, which would give lots
> of false sharing on pentium.
> Kumon, could you check that that is not the case ?
> At least for Williamette with bigger cache lines it prevents us from having
> a single SMP kernel (or otherwise it requires wasting a lot of memory)
> Seems the times for single binary SMP kernel are over with 2.4.

Depends on your performance needs. We can probably build a single SMP kernel
with a bit of extra padding that works ok on all.

The K7 already has 64byte cache lines so we know BYTES is 64 works 8)

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This archive was generated by hypermail 2b29 : Wed Jun 07 2000 - 21:00:21 EST