For all the folks out there having problems with timing errors and general
problems in having DMA (specifically Ultra DMAing), I have a new data
point from an industry meeting that was held today (April 10th).
It appears that verification from manucaturers and owners of the UDMA
technology patent have noted the short comings of the "electronics" and
"signal" stablity based upon different data clocking states. Some of this
is a direct result of OEM failing to adjust the limiting shew offsets
between the host and the device and potential crosstalk. This may be a
real issue; HOWEVER........
Many of the signal traces displayed signal contamination due to JUNK/DIRTY
power supplies.
If you have a standard chipset that is supported and you know of others
with your exact setup that runs and yours fails..........
Check your PowerSupply!
I will try to extract the safe ranges that levels can vary and the noise
limits, but this is a very serious issue that has had no probable solution
until know. If you have a clean power supply and it still is an issue,
we need to address the IDC connection point!
This is a hardware issue that there is nothing that the OS can do to solve
the problem............:-(
Andre Hedrick
The Linux ATA/IDE guy
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