Re: Timestamp counters on SMP

From: Vojtech Pavlik (vojtech@suse.cz)
Date: Fri Mar 31 2000 - 17:40:14 EST


On Fri, Mar 31, 2000 at 12:59:44PM -0800, H. Peter Anvin wrote:

> > > > there are notebooks which change the CPU speed and voltage (and the TSC
> > > > speed as well), depending on the load. This is a much bigger problem.
> > >
> > > Current x86 notebooks dont change the TSC speed. They change the clock duty
> > > cycle not the clock rate.
> >
> > That is not true!
> >
> > I have two different notebooks (toshiba satellite 4030cdt and ibm
> > thinkpad), both of them change tsc speed (log from toshiba:)
> >
> > Mar 29 23:35:22 bug apmd[72]: Now using Battery Power
> > Mar 29 23:35:22 bug apmd[72]: Battery: * * * (100% 2:22)
> > Mar 29 23:40:06 bug kernel: TSC is slower than it should be! Detected
> > 151955503 Hz processor.
> > Mar 29 23:40:07 bug kernel: TSC is faster than it should be! Detected
> > 299947489 Hz processor.
>
> This is bad design. It means the TSC is useless on that system.

Anyway, this proves that there indeed are such notebooks that don't
change just the duty cycle, but also the clock. And, it also means that
the kernel should take this into account. While I think it's not very
likely we can compensate for it (remeasure the TSC speed after every
APM/ACPI call?), we should at least be able to detect it somehow and
disable the use of TSC in the case its speed varies.

Or at least issue a warning, like Pavel's kernel does, so that the user
notices the problem and disables TSC in the kernel config. I suppose
most users live with this unnoticed and causing problems.

-- 
Vojtech Pavlik
SuSE Labs

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