Re: Timestamp counters on SMP

From: Richard B. Johnson (root@chaos.analogic.com)
Date: Tue Mar 28 2000 - 12:42:34 EST


On Tue, 28 Mar 2000, Krisztian Flautner wrote:

>
>
> Hello,
>
> I would like to know whether (and how) the timestamp counters
> of multiple CPUs in a multiprocessor machine are synchronized.
> Can I rely on the fact that if I check the TSC value on
> cpu 0 and then on cpu 1, then the second number will be
> larger than the first?
>
> Do the counters drift or do they stay in synch once synchronized?
>
>
> Thanks, -- Kris
>

You cannot count on bit-granularity. However, except for some bad mother
boards, you can count on them being very close, so close that the
overhead necessary to read the value will assure that a second read
from it, or any other, does show an increased value. This has been
discussed before, several years ago, when SMP machines were just
coming out.

The bad mother boards have the problem that the CPU clock (which is
shared by all CPUs), did not start before the reset line went false.
This meant that T(0) for each CPU started whenever the slowly-increasing
clock level was sufficient to clock the chip. This is different for
different chips. The solution is to make sure the clock is running
before the CPUs get hit with a reset. Even then, the affect of the
reset, and when it starts the internal PLL, will be slightly different
for different chips. This will result in a few cycles difference
in actual internal clock-counts. However, since reading the chip
takes time, you should never see non-monotonic behavior at the software
level.

Cheers,
Dick Johnson

Penguin : Linux version 2.3.41 on an i686 machine (800.63 BogoMips).

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/



This archive was generated by hypermail 2b29 : Fri Mar 31 2000 - 21:00:22 EST