Hi,
I'm the guy that asked if anyone had gotten the 440BX (PIIX4)
to use UDMA. I kept getting DMA timeouts. I was able to kinda
get it to work...read on.
>From what everyone reported back (thanks everyone), there was no
clear pattern. MAXTORs seem to always work, IBMs too. To some,
this indicates Seagate and Western Digital are broken. But, I
haven't heard of problems with these drives when other chipsets
are used. Maybe I haven't listened hard enough?
Anyway, I got a copy of the 82371AB manual (29056201.pdf, just
search for 82371AB on http://www.intel.com/, developer section.
It's one of the first datasheets listed.)
There's a table on page 98 which maps the CT values set in regs
4a and 4b to the different modes, and associated UDMA timings.
CT==00, 120ns, mode 0, CT==01, 90 ns, mode 1, CT == 10, 60 ns,
mode 2.
Now, my hdparm -i /dev/hda says:
/dev/hda:
Model=ST39140A, FwRev=841260, SerialNo=AY073758
Config={ HardSect NotMFM HdSw>15uSec Fixed DTR>10Mbs }
RawCHS=16383/16/63, TrkSize=38430, SectSize=610, ECCbytes=4
BuffType=3(DualPortCache), BuffSize=448kB, MaxMultSect=16, MultSect=16
DblWordIO=no, maxPIO=2(fast), DMA=yes, maxDMA=2(fast)
CurCHS=16383/16/63, CurSects=-66060037, LBA=yes
LBA CHS=1023/256/63 Remapping, LBA=yes, LBAsects=17803440
tDMA={min:120,rec:120}, DMA modes: mword0 mword1 mword2
IORDY=yes, tPIO={min:120,w/IORDY:120}, PIO modes: mode3 mode4
UDMA modes: mode0 mode1 *mode2
with tDMA the DMA timings. So, I thought perhaps, even though
the drive claims to be udma mode 2 capable, maybe the DMA timing
should be 120ns. So, I forced this into reg4a and reg4b.
The result is: it works. I am able to use UDMA for the first
time ever. hdparm -t (and dd ...) times are about 13.5 MB/s,
about what you would expect. System time is kinda high.
I've included my notes on lspci -xxxbs 00:04.1. The following
does not show 4a and 4b == 0.
Thoughts? comments? Maybe tDMA as reported by hdparm isn't
even related to the mode values and my drive just doesn't work at
mode2 like it should? I'm very new to the wonderful world of IDE.
All tests were run on 2.2.15pre14, with the latest ide patch.
To force reg4a and 4b, all I did was edit piix.c, writing:
(line 339)
if (speed >= XFER_UDMA_0) {
if (!(reg48 & u_flag))
pci_write_config_word(dev, 0x48, reg48|u_flag);
/*
if (!(reg4a & u_speed)) {
pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
pci_write_config_word(dev, 0x4a, reg4a|u_speed);
}
*/
reg4a = 0;
printk( "PIIX4: Forcing 0x4a-0x4b to 0x%4.4x.\n", reg4a );
pci_write_config_word(dev, 0x4a, reg4a);
if (speed > XFER_UDMA_2) {
if (!(reg54 & v_flag)) {
....
This is not a patch because this is not a fix...also, I got the
same results on 2.3.99pre2.
My notes on lspci -xxxbs 00:04.1
00:04.1 IDE interface: Intel Corporation 82371AB PIIX4 IDE (rev 01)
00: 86 80 -- Vendor
02: 11 71 -- Device
04: 05 00 -- Busmaster (BME, IOSE=1)
06: 80 02 -- PCI status (Fast back-to-back,
DEVSEL# timing status, DEVT, medium timing
After a hang, we should be able to get
some stuff from here.
08: 01 -- Revision - stepping
09: 80 01 01 00 -- Busmaster cap, IDE controller, mass storage device
0d: 20 -- MLTC==2, Master latency timer count value, linked to
PHLDA#
0e: 00 -- Header type reg.
0f: 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 d8 00 00 -- Bus master interface base address reg. d800.
16 byte IO address space address
24: 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40-41: Primary channel
42-43: Secondary channel
40: 07 a3 IDE decode enable
1010 0011 0000 0111
42: 70 c0
1100 0000 0111 0000
If the bits are device specific, we talk about the CD
for drive 1 (42-43) and for drive 0, the HD (40-41)
(hda = hard drive, hdd = cdrom on my system)
15: IDE decode enable
14: Slave IDE timing register enable (SITRE)
(disabled on primary cause we don't have a slave)
13:12 IORDY Sample Point (ISP)
10 = 3 clocks
00 = 5 clocks
9:8 Recovery time (RTC)
11 = 1 clock
00 = 4 clocks
7 DMA timing enable only (DTE1)
1 = fast timing only for DMA
6 Prefetch and post enable (PPE1) - slave
enabled on CD - ide1
5 IORDY sample point enable drive select 1 (IE1)
enabled on CD
4 Fast timing bank drive select 1 (TIME1)
enabled on CD - ide1
3 DMA timing enable only (DTE0), both DMA and PIO use fast
enable on HDA (well, 0 == enable)
2 PPE0
set on HD
1 IORDY
set on HD
0 TIME0
Fast timing set on HD.
44: 38 Slave IDE timing register.
SISP1 = 5 clocks
SRTC1 = 1 clocks
45: 00 00 00
UDMA control register -- This is how to tell if we are in
UDMA or not!
48: 09 enable UDMA for sec. drive 1 and prim drive 0.
SSDE1, PSDE0.
49: 00
UDMATIM -- UDMA timing register
4a: 02 20
13:12 = 10 = CT=2 PCICLK, RP=4 PCICLK, sec drive 1
1:0 = 10 = CT=2 PCICLK, RP=4 PCICLK, prim drive 0
CT = minimum data write strobe cycle time and minimum
read to pause time.
From table 13: CT=10 is a 60 ns strobe period.
But, info from the drive suggests CT==00 might be more approp.
Well, maybe. What is tDMA as reported by hdparm? How
does it relate to setting up the PIIX4?
4c: 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00
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