On Mon, 28 Feb 2000, Alan Cox wrote:
> All the x86 cpu SMP machines have synchronized busses so the TSC rate is
> the same (so far anyway) but the TSC start on a few machines varies. 2.2.15pre
> is quite happy on such a board but the code hasnt been rewritten for 2.3.x
> as far as I know.
The TSC operates at the core cpu rate not busrate AFIK. The user I was
replying to was running both a 400 (4x100) and a 450 (4.5x100). Since the
PII/III have locked multipliers the system was actually running with two
differnt CPU speeds (he said he was and insisted that this was okay).
So, the rate there is indeed differnt. Not a good thing. :)
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This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 21:00:19 EST