Ingo Molnar writes:
> On Thu, 24 Feb 2000, Artur Skawina wrote:
>
> > > same. But the local APIC can be disabled on RESET in Pentium chips and by
> > > software means on P6 CPUs. Once disabled it cannot be enabled till the
> > > next RESET.
> >
> > p6_enable_apic()
> > {
> > unsigned rl, rh;
> >
> > rdmsr( 27, rl, rh );
> > wrmsr( 27, rl^(1<<11), rh );
> > }
>
> does this always work? I believe there is some pin that disables the APIC
> permanently - is this really the case?
To enable the local APIC on UP P6:
1. set the enable bit (1<<11) in MSR 0x1B; this is documented in the IA32 manuals.
2. map it (set_fixmap(FIX_APIC_BASE, APIC_PHYS_BASE))
3. init it to through-local mode (LVT0 as ExtINT, LVT1 as NMI, mask LVTT/LVTPC/LVTERR)
The disable pin only exists on P5. According to the Pentium spec update, there's a magic
flag in TR12 (I think) on certain P5 steppings which allows the local APIC to be disabled
(as an errata workaround), but I don't know if it works the other way as well.
> anyway, in 2.5 we can explore this stuff - right now we already have
> IO-APIC on UP, and a trivial patch enables compiling APIC support but no
> IO-APIC.
Would you accept a patch which allows CONFIG_X86_LOCAL_APIC && !CONFIG_X86_IO_APIC?
Also, which interrupt should we use for LVTPC? Last time I checked, there wasn't
room for another APIC interrupt without violating the "at most two interrupts
per priority level" rule.
/Mikael
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 21:00:12 EST