On Wed, Feb 09, 2000 at 02:59:41AM +0100, Ingo Molnar wrote:
>
> you need a system equipped with an IO-APIC (either SMP system, or UP
> system with IOAPIC). Then any IRQ source (or more) can be marked to be
> delivered to the NMI pin - sorting out which IRQ is which is a different
> matter. If only one IRQ is redirected to NMI then it's not a problem. A
> redirected IRQ is dedicated to be NMI, so it will not show up in the
> do_IRQ() path.
>
> so it's a special case, and for the 'generic ISA box' case it's not
> possible without extra hardware. (but the extra hardware to generate
> periodic NMI interrupts is not expensive at all)
>
I've been thinking of ideas like this for multiple-priority interrupts,
a la RTLinux, although I would prefer to see it integrated into the
kernel. One idea I had was to set the APIC_LDR mask of cpu #0 to
0x03, cpu #1 to 0xc0, etc., and then set the destination mask for
higher priority interrupts to 0xff, and low priority interrupts to
0x55. Then to disable low priority interrupts, a cpu would set its
APIC_LDR mask to 0x02 (or 0x08). Unfortunately, I don't know if this
is legal and/or fast enough. I'm hoping you might shed some light.
Actually doing the coding and testing it has not been given a time
slice in several weeks.
I have, however, written a dual-priority patch for the i8259.
Originally, it touched the i8259 every time a 'cli()' was done,
which was butt-slow. Now, however, it touches the i8259 only
when it _really_, __really__ needs to (basically only when it
needs to avoid IRQ floods), which means that it touches the
i8259 even less than stock 2.3.42.
dave...
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